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OKI Semiconductor ML9361
128-Channel Organic EL Anode Driver
PEDL9361-01
Issue Date:Dec. 12, 2002
Preliminary
GENERAL DESCRIPTION
The ML9361 is an organic EL anode driver LSI with 128 drivers. The anode driver is constant current output type and allows adjustment of current and pulse width for each output. Since this LSI has the output condition setting function, which allows setting of all outputs High, all outputs Low, and all outputs High Impedance, the user can set driving methods suited to the characteristics of individual organic EL panel. When combined with ML9371 the organic EL cathode driver, the ML9361 can drive a 64 x 128 full-dot panel.
FEATURES
* * * * * * * * * * 3.0 to 5.5 V 8.0 to 30 V (max.) 128 outputs -1.0 mA (constant current output, current adjustment range = at 100%) Anode low output current : 40 mA (max.) Anode low ON-resistance : 500 (max.) Anode output current adjustment range : 0%, 33%, 66%, and 100% (for each output) Output pulse width adjustment : Adjustable in 16 different degrees (adjusted by external clock input, for each output) All outputs High, all outputs Low, and all outputs High Impedance can be set as output conditions Package : Gold bump chip (TCP is tailored for each customer requirement) Logic power supply voltage EL drive voltage Anode outputs Anode high output current : : : :
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BLOCK DIAGRAM
OUT1 VDISP VEL VELSEL R-ADJ D-GND VDD HZ ALL H ALL L OFF HZ A0 HZ PL A-CLK RESET Constant current source circuit OUT128
Anode driver
Driver control circuit
STB RESET
PAO0-1 PAO2-1 PAO1-1 PAO3-1 PAI0-1 PAI2-1 PAI1-1 PAI3-1 PO0-1 PO2-1 PO1-1 PO3-1
PAO0-128 PAO2-128 PAO1-128 PAO3-128 PAI0-128 PAI2-128 PAI1-128 PAI3-128 PO0-128 PO2-128 SO0 PO1-128 PO3-128 SO1 SO2 data shift register SO3
Pulse width adjustment data latch
PADJ0-I/O PADJ1-I/O PADJ2-I/O PADJ3-I/O
SI0 SI1 SI2 SI3 CLK RESET F/R
Pulse width adjustment
PADJ0-O/I PADJ1-O/I PADJ2-O/I PADJ3-O/I
STB
IAO0-1 IAO1-1 STB RESET IAI0-1 IAI1-1 PO4-1 SI4 PO5-1 SI5 CLK RESET F/R
IAO0-128 IAO1-128
Current adjustment data latch
IAI0-128 IAI1-128 PO4-128 PO5-128
IADJ0-I/O IADJ1-I/O D-CLK F/R L-GND
Current adjustment data shift register
SO4 SO5
IADJ0-O/I IADJ1-O/I
PIN CONFIGURATION (Gold bump chip)
OUT2 OUT1 OUT3 OUT4 OUT5 OUT124 OUT126 OUT128 OUT125 OUT127
VDISP VDISP VDISP D-GND D-GND D-GND
VDISP VDISP
ML9361
VDISP D-GND D-GND D-GND
R-ADJ D-CLK PADJ0-I/O PADJ2-I/O IADJ0-I/O VDD ALL H OFF HZ PL VELSEL RESET IIADJ1-O/I PADJ3-O/I PADJ1-O/I VEL STB PADJ1-I/O PADJ3-I/O IADJ1-I/O HZ ALL L A0 HZ A-CLK L-GND IADJ0-O/I PADJ2-O/I PADJ0-O/I F/R
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PIN DESCRIPTION
Symbol VDISP VDD D-GND L-GND VEL I/O Description VDISP is a power supply pin for anode driver circuit and constant current source circuit. VDD is the logic circuit power supply pin. Power supply D-GND is a ground pin for anode driver circuit and constant current source circuit. L-GND is a ground pin for logic circuit. D-GND and L-GND should be connected outside the LSI. OUT1 to OUT128 output current setting voltage input pin. Power supply Input voltage to this pin is enabled when VELSEL is high, and disabled when it is low. Leave this pin open or input a voltage within the guaranteed operating range. Pin for selecting the output current adjusting voltage for anode driver circuit. Microcontroller * When this pin is low, LSI's internal voltage (5 V) is selected. * When this pin is high, the input voltage at the VEL pin is selected. OUT1 to OUT128 output current setting resistor connection pin. Resistor Data transfer direction select signal input pin for current adjusting data shift register and pulse width adjusting data shift register. Microcontroller * When this pin is low, data is transferred starting at POn-1 toward POn-128. (n = 1 to 5) * When this pin is high, data is transferred starting at POn-128 toward POn-1. (n = 1 to 5) Anode output current adjusting data input-output pins. When the F/R pin is low, these pins are input pins and data is read into at the rising edge of D-CLK. When the F/R pin is high, these pins are output pins and the output status Microcontroller, changes at the falling edge of D-CLK. or ML9361 on Anode output current adjusting data input-output pins. next stage When the F/R pin is high, these pins are input pins and data is read into at the rising edge of D-CLK. When the F/R pin is low, these pins are output pins and the output status changes at the falling edge of D-CLK. Connected to Anode output pulse width adjusting data input-output pins. When the F/R pin is low, these pins are input pins and data is read into at the rising edge of D-CLK. When the F/R pin is high, these pins are output pins and the output status Microcontroller, changes at the falling edge of D-CLK. or ML9361 on next stage Anode output pulse width adjusting data input-output pins. When the F/R pin is high, these pins are input pins and data is read into at the rising edge of D-CLK. When the F/R pin is low, these pins are output pins and the output status changes at the falling edge of D-CLK. Anode output current adjusting data and anode output pulse width adjusting data transfer Microcontroller clock input pin (Schmitt input) Anode output current adjusting data and anode output pulse width adjusting data latch Microcontroller strobe signal input pin (Schmitt input) Initialization signal input pin. When this pin is set low, the LSI enters the following initial setting states: Microcontroller * Shift register outputs and latch outputs: all "low" * All anode drive signal outputs: "high impedance" Input pin for anode drive signal output control signal. Microcontroller When this pin is low, all anode drive signal outputs are high impedance. Input pin for anode drive signal output control signal (Schmitt input). Microcontroller When this pin is high, all anode drive signal outputs are constant current output. Input pin for anode drive signal output control signal (Schmitt input). Microcontroller When this pin is high, anode drive signal outputs are all low. Input pin for anode drive signal output control signal. Microcontroller Used to set the anode drive signal output condition at the time that is OFF to either low or high impedance with the combination of A0 HZ, P L, and anode output pulse width adjusting data. Input pin for anode drive signal output control signal. Microcontroller Used to set the anode drive signal output condition at the time that dot is OFF to either low or high impedance with the combination of OFF HZ, P L, and anode output pulse width adjusting data. Input pin for anode drive signal output control signal (Schmitt input). Microcontroller Used to set the anode drive signal output condition at the time that dot is OFF to either low or high impedance with the combination of OFF HZ, A0 HZ, and anode output pulse width adjusting data. Microcontroller Anode output pulse width adjusting clock input pin (Schmitt input). Organic EL Anode drive signal output pins for organic EL. anode
--
I
VELSEL R-ADJ F/R
I I I
IADJ0-I/O IADJ1-I/O IADJ0-O/I IADJ1-O/I PADJ0-I/O PADJ1-I/O PADJ2-I/O PADJ3-I/O PADJ0-O/I PADJ1-O/I PADJ2-O/I PADJ3-O/I D-CLK STB RESET
I/O
O/I
I/O
O/I
I I
I
HZ ALL H ALL L
I I I
OFF HZ
I
A0 HZ
I
PL A-CLK OUT 1 to 128
I I O
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FUNCTION TABLE
1. Operation during Transfer of Anode Output Current Adjusting Data and Anode Output Pulse Width Adjusting Data * When F/R is low
Input PADJ RESET D-CLK m-I/O, IADJ n-I/O L X X L H L H X L L L L L L X H L L H L PO k-1 PO k-1 L PO k-126 PO k-126 Invariable Invariable Invariable Invariable PO k-1 PO k-2 L PO k-127 PO k-127 STB PO k-1 PO k-2 PO k-127 PO k-128 Shift Register PAO m-1, IAO n-1 L PAO m-2, IAO n-2 L Invariable Invariable Invariable Invariable Invariable PO k-127 PO k-128 Latch PAO m-127, IAO n-127 L PAO m-128, IAO n-128 L Output PADJ m-O/I, IADJ n-O/I L Invariable Invariable PO k-128 PO k-128 Invariable Invariable
H
m = 0 to 3
n = 0, 1
k = 0 to 5
2. Operation during Transfer of Anode Output Current Adjusting Data and Anode Output Pulse Width Adjusting Data * When F/R is high
Input PADJ RESET D-CLK m-O/I, IADJ n-O/I L X X L X L L L L PO k-128 PO k-128 L PO k-3 PO k-3 L PO k-2 PO k-2 STB PO k-128 PO k-127 PO k-2 PO k-1 Shift Register PAO PAO Latch PAO m-2, IAO n-2 L Invariable PAO m-1, IAO n-1 L Output PADJ m-I/O, IADJ n-I/O L Invariable
m-128, m-127, IAO n-128 L IAO n-127 L
H
L
H
Invariable
Invariable PO k-1 PO k-1 Invariable PO k-1 Invariable
H
L
L
Invariable
Invariable
H
L L
Invariable Invariable Invariable PO k-128 PO
Invariable Invariable PO k-2
L
X H
k-127
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3. Operation of Output Section
HZ L ALL H X H ALL L X X H OFF HZ X X X A0 HZ X X X PL X X X L L X H H L H L H L L L H H H L H L H H L COMP OUTn X X X H L PWM Data n X X X X X One of PWM data n is "H" All "L" X One of PWM data n is "H" All "L" One of PWM data n is "H" All "L" X One of PWM data n L is "H" All "L" One of PWM data n is "H" All "L" OUTn High impedance Constant current output Low Constant current output Low Low High impedance Constant current output High impedance Low Low High impedance Constant current output High impedance High impedance Low High impedance
L
H
Note:
When setting the STB pin to a high level, do so only when both the HZ pin and the ALL L pin are high or both are low.
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OUTPUT WAVEFORMS
1. When OFF HZ, A0 HZ, and P L are all low
RESET HZ ALL H ALL L OFF HZ A0 HZ PL PWM DATAm PWM DATAn D-CLK STB A-CLK OUTm OUTn
HZ HZ L L L L L L H H
L L L
Data: 4 Data: 15
Data: 4 Data: 0
Data: 4 Data: 0
2. When OFF HZ is high and A0 HZ and P L are low
RESET HZ ALL H ALL L OFF HZ A0 HZ PL PWM DATAm PWM DATAn D-CLK STB A-CLK OUTm OUTn
HZ HZ HZ HZ L L L HZ H H
H L L
Data: 4 Data: 15
Data: 4 Data: 0
Data: 4 Data: 0
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3. When OFF HZ and A0 HZ are high and P L is low
RESET HZ ALL H ALL L OFF HZ A0 HZ PL PWM DATAm PWM DATAn D-CLK STB A-CLK OUTm OUTn
HZ HZ HZ HZ L L HZ HZ H H
H H L
Data: 4 Data: 15
Data: 4 Data: 0
Data: 4 Data: 0
4. When OFF HZ and A0 HZ are low and P L is controlled by pulse
RESET HZ ALL H ALL L OFF HZ A0 HZ PL PWM DATAm PWM DATAn D-CLK STB A-CLK OUTm OUTn
HZ HZ L L L L L HZ L L H H
L L L
Data: 4 Data: 15
Data: 4 Data: 0
Data: 4 Data: 0
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5. When OFF HZ is high, A0 HZ is low, and P L is controlled by pulse
RESET HZ ALL H ALL L OFF HZ A0 HZ PL PWM DATAm PWM DATAn D-CLK STB A-CLK OUTm OUTn
HZ HZ HZ HZ HZ HZ L HZ L HZ H H
H L L
Data: 4 Data: 15
Data: 4 Data: 0
Data: 4 Data: 0
6. When OFF HZ and A0 HZ are high and P L is controlled by pulse
RESET HZ ALL H ALL L OFF HZ A0 HZ PL PWM DATAm PWM DATAn D-CLK STB A-CLK OUTm OUTn
HZ HZ HZ HZ HZ HZ L HZ HZ HZ H H
H H L
Data: 4 Data: 15
Data: 4 Data: 0
Data: 4 Data: 0
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ABSOLUTE MAXIMUM RATINGS
Parameter Logic power supply voltage EL drive power supply voltage (anode) Logic input voltage Logic output voltage EL output current adjustment voltage EL driver output voltage EL driver output voltage (pulse)*1 EL driver output current Storage temperature Symbol VDD VDISP VIN VOUT VEL VOUT-EL VOUT-ELP IELH (source) IELL (sink) Tstg Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 25C Applied to OUT1 to OUT128 Applied to OUT1 to OUT128 Applied to OUT1 to OUT128 -- Rating -0.3 to +6.5 -0.3 to +35 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VDISP + 0.3 -0.3 to VDISP + 0.3 -VDISP to 2 x VDISP -1.5 50 -40 to +125 Unit V V V V V V V mA mA C
*1 Consult Oki for customization of pulse width.
RECOMMENDED OPERATING CONDITIONS
Parameter Logic power supply voltage EL drive power supply voltage (anode) Logic input voltage EL output current adjustment voltage Symbol VDD VDISP VIN VEL Condition -- -- -- -- Applied to OUT1 to OUT128 Current adjustment range = 100% Applied to OUT1 to OUT128 -- Range 3.0 to 5.5 8 to 30 0.0 to VDD 4 to VDISP - 3 Unit V V V V
IELH (source) EL driver output current IELL (sink) Junction operating temperature Tjop
-0.1 to -1.0
mA
0 to 40 -40 to +125
mA C
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ELECTRICAL CHARACTERISTICS
DC Characteristics 1
VDD = 3.0 to 5.5 V, VDISP = 8 to 30 V, Tjop = -40 to +125C
Parameter "H" input voltage "L" input voltage Schmitt voltage width Symbol VIH VIL VSH Applicable Pins All input pins All input pins D-CLK, A-CLK, STB, A-CLK, ALL H, ALL L Inputs other than RESET, HZ, ALL H, ALL L, VELSEL, and F/R RESET, HZ, ALL H, ALL L, VELSEL, F/R Inputs other than RESET, HZ, ALL H, ALL L, VELSEL, and F/R RESET, HZ, ALL H, ALL L, VELSEL, F/R PADJm-I/O, PADJm-O/I, IADJn-I/O, IADJn-O/I PADJm-I/O, PADJm-O/I, IADJn-I/O, IADJn-O/I Condition -- -- VDD = 5.0 V VDD = 5.5 V VI = 5.5 V VDD = 5.5 V VI = 5.5 V VDD = 5.5 V VI = 0.0 V VDD = 5.5 V VI = 0.0 V VDD = 3.0 V IO = -200 A VDD = 3.0 V IO = 200 A VDISP = 24 V VEL = VO = 15 V VELSEL = high R-ADJ = 30 k Current adjustment range = 100% VDISP = 24 V VEL = VO = 15 V VELSEL = high R-ADJ = 30 k Current adjustment range = 66% VDISP = 24 V VEL = VO = 15 V VELSEL = high R-ADJ = 30 k Current adjustment range = 33% VDISP = 24 V VEL=VO = 7.5 V VELSEL = high R-ADJ = 60 k Current adjustment range = 100% VDISP = 24 V VEL = VO = 7.5 V VELSEL= high R-ADJ = 60 k Current adjustment range = 66% VDISP = 24 V VEL = VO =7.5 V VELSEL = high R-ADJ = 60 k Current adjustment range = 33% Min. 0.8VDD 0 0.4 Typ. -- -- 1.0 Max. VDD 0.2VDD 1.6 Unit V V V A
IIH1 "H" input current IIH2
-10
--
10
40
100
200
A
IIL1 "L" input current IIL2
-10
--
10
A
-10
--
10
A
"H" output voltage
VOH
0.8VDD
--
--
V
"L" output voltage
VOL
--
--
0.2VDD
V
Anode driver ON current 1
IELON1
OUT1 to OUT128
-465 (-7%)
-500
-535 (+7%)
A
Anode driver ON current 2
IELON2
OUT1 to OUT128
-306 (-7%)
-330
-353 (+7%)
A
Anode driver ON current 3
IELON3
OUT1 to OUT128
-153 (-7%)
-165
-177 (+7%)
A
Anode driver ON current 4
IELON4
OUT1 to OUT128
-112 (-10%)
-125
-138 (+10%)
A
Anode driver ON current 5
IELON5
OUT1 to OUT128
-74 (-10%)
-82.5
-91 (+10%)
A
Anode driver ON current 6
IELON6
OUT1 to OUT128
-37.5 (-12%)
-41.25
-46 (+12%)
A
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DC Characteristics 2
VDD = 3.0 to 5.5 V, VDISP = 8 to 30 V, Tjop = -40 to +125C
Parameter Symbol Applicable Pins Condition VDISP = 24 V VO = 15 V VELSEL = low R-ADJ = 10 k Current adjustment range = 100% VDISP = 24 V VO = 15 V VELSEL = low R-ADJ = 10 k Current adjustment range = 66% VDISP = 24 V VO = 15 V VELSEL = low R-ADJ = 10 k Current adjustment range = 33% VDISP = 8 V VO = 8 V VDISP = 30 V VO = 30 V VDISP = 8 V VO = 1 V VDISP = 17 to 30 V VEL = VO = 15 V R-ADJ = 30 k Current adjustment range = 100% VDISP = 24 V VEL = 15 V VO = 8 to 21 V R-ADJ = 30 k Current adjustment range = 100% VDISP = 24 V VEL = VO = 15 V R-ADJ = 30 k Current adjustment range = 100% VDISP = 24 V VEL = VO = 15 V R-ADJ = 30 k Current adjustment range = 100% OUT1 to OUT128 = "ON" Inside one chip. VDISP = 24 V VEL = VO = 15 V R-ADJ = 30 k Current adjustment range = 100% OUT1 to OUT128 = "ON" Inside one chip. VDISP = 24 V VEL = VO = 15 V R-ADJ = 30 k Current adjustment range = 100% OUT1 to OUT128 = "ON" Inside one chip. Min. Typ. Max. Unit
Anode driver ON current 7
IELON7
OUT1 to OUT128
-415 (-17%)
-500
-585 (+17%)
A
Anode driver ON current 8
IELON8
OUT1 to OUT128
-274 (-17%)
-330
-386 (+17%)
A
Anode driver ON current 9
IELON9
OUT1 to OUT128
-137 (-17%)
-165
-193 (+17%)
A
Anode driver low output current 1 Anode driver low output current 2 Anode driver low output current 3 VDISP dependence coefficient for anode driver ON current *1 VO dependence coefficient for anode driver ON current *2
IELL1 IELL2 IELL3
OUT1 to OUT128 OUT1 to OUT128 OUT1 to OUT128
16 60 500
-- -- --
-- -- --
mA mA A
IELON1
OUT1 to OUT128
-2.5
0
2.5
%/V
IELON2
OUT1 to OUT128
-2.5
0
2.5
%/V
Temperature coefficient for anode driver ON current
IELON3
OUT1 to OUT128
-0.1
0
0.1
%/C
Relative error between dots (excluding adjoining dots) for anode driver ON current
IELON4
OUT1 to OUT128
-5
0
5
%
Tilt inside chip for anode driver ON current *3
IELON5
OUT1 to OUT4 OUT63 to OUT66 OUT125 to OUT128
-3
0
3
%
Relative error between adjoining dots for anode driver ON current *4
IELON6
OUT1 to OUT128
-2
0
2
%
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*1
VDISP dependence coefficient depends on the following conditions: I(VDISP = nV): Anode driver ON current at VDISP = nV. IELON1 = [ I(VDISP = nV) - I(VDISP = (n+1)V) ]/{ [ I(VDISP = nV) + I(VDISP = (n+1)V) ]/2 } x 100 VO dependence coefficient depends on the following conditions: I(VO = nV): Anode driver ON current at VO = nV. IELON2 = [ I(VO = nV) - I(VO = (n-1)V) ]/{ [ I(VO = nV) + I(VO = (n-1)V) ]/2 } x 100 Tilt inside chip depends on the following conditions: Cave: Average output current of OUT1 to 4, OUT63 to 66, and OUT125 to 128. Lave: Average output current of OUT1 to 4. Rave: Average output current of OUT125 to 128. IELON5 = (Lave - Cave)/Cave IELON5 = (Rave - Cave)/Cave A relative error between adjoining dots depends on the following condition: (IELON(N+1) - IELON(N))IELON(N)
*2
*3
*4
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Supply Current
VDD = 3.0 to 5.5 V, VDISP = 8 to 30 V, Tjop = -40 to +125C
Parameter Symbol Applicable Pins Condition VDISP = 30 V VEL = 15 V A-CLK = 5 MHz R-ADJ = 30 k Current adjustment range = 100% Output = open PWM data = other than "0" VDD = 0 V VDISP = 30 V VEL = 15 V R-ADJ = 30 k Output = open VDD = 5.5 V D-CLK = 5 MHz DATA = "1010.....10" VDD = 5.5 V D-CLK, A-CLK = 5 MHz DATA = "1010.....10" VDD = 5.5 V A-CLK = 5 MHz DATA = "1010.....10" VDD = 5.5 V, D-CLK = halted RESET = 0 V All the other inputs are also 0 V. Min. Typ. Max. Unit
IDISP1
VDISP
--
--
5.0
mA
IDISP2
VDISP
--
--
300
A
Supply current VDD
--
--
18
mA
IDD1
VDD
--
--
20
mA
VDD
--
--
5
mA
IDD2
VDD
--
--
100
A
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AC Characteristics
VDD = 3.0 to 5.5 V, VDISP = 8 to 30 V, Tjop = -40 to +125C Parameter D-CLK frequency D-CLK pulse width A-CLK frequency A-CLK pulse width DATAD-CLK setup time D-CLKDATA hold time STB pulse width ALL LSTB setup time STBALL L hold time HZSTB setup time STBHZ hold time ALL LD-CLK setup time D-CLKALL L hold time ALL LA-CLK setup time A-CLKALL L hold time P L pulse width P LALL L setup time STBP L setup time D-CLKSTB hold time RESET pulse width RESET execution time A-CLK output delay time Input signal rise/fall time Symbol fDCLK tDCW fACLK tACW tDS Applicable pins D-CLK D-CLK A-CLK A-CLK D-CLK IADJn-I PADJm-I D-CLK IADJn-I PADJm-I STB ALL L, STB ALL L, STB HZ, STB HZ, STB ALL L, D-CLK ALL L, D-CLK ALL L, A-CLK ALL L, A-CLK PL ALL L, P L P L, STB D-CLK STB RESET RESET HZ, ALL H ALL L, P L A-CLK OUT1 to 128 All inputs Condition -- -- -- -- -- Min. 0 50 0 50 50 Typ. -- -- -- Max. 5.0 -- 5.0 -- -- Unit MHz ns MHz ns ns
tDH tSTBW tALSS tSALH tHZSS tSHZH tALDCS tDCALH tALACS tACALH tPLW tPLALS tSTPLS tDCSH tRW tRSON tDr tDf tr tf
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
50 50 100 100 100 100 100 100 100 100 100 100 100 50 100 250
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
--
--
--
2.0
s
--
--
--
500
ns
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TIMING DIAGRAM
Data Input
VDD
0.9VDD
tRSON
tRW VIH VIL
RESET
ALL L
VIH VIL tALDCS VIH VIL tDS tDH VIH VIL tDCSH tSTBW 1/fDCLK tDCW tDCALH
D-CLK
IADJn-I/O IADJn-O/I PADJm-I/O PADJm-O/I STB
ALL L
VIH VIL tALACS 1/fACLK tACW tACALH VIL
A-CLK
VIH VIL tALSS tSALH
STB
tSHZH
HZ PL
VIL
VIH tPLW VIH VIL
tHZSS
tSTPLS
STB
tr All inputs
tf
0.9VDD 0.1VDD
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DESCRIPTION OF OPERATION
Initial Settings Following initial settings can be made by setting the RESET pin to low. * The shift register outputs and latch circuit outputs become all low. * Anode drive signal output pins (OUT1 to 128) become high impedance. Anode Output Current Adjustment 1. Output current adjustment for entire output Output current of anode drive signal output pins (OUT1 to OUT128) can be adjusted, as a batch adjustment for all the output pins. Output current is adjusted by varying the value of the resistor connected between the R-ADJ pin and GND. Output current (typ.) at the time that the VELSEL pin is "high" and "low" is given by the following expressions: [When the VELSEL pin is "high"] Output current (typ.) = VEL pin voltage / R-ADJ resistance value [When the VELSEL pin is "low"] Output current (typ.) = 5 V / R-ADJ resistance value 2. Output current adjustment for each output Output current of anode drive signal output pins (OUT1 to OUT128) can be adjusted for each output pin. Adjustment of each output current is made by bit data IADJ0-n and IADJ1-n. This 2-bit data is written in the shift register at the rising edge of the D-CLK signal and latched at the rising edge of the STB signal. Relation between IADJ0-n, IADJ1-n, and output current is shown below.
IADJ1-n 0 0 1 1 IADJ0-n 0 1 0 1 Current adjustment range 0% 33% 66% 100%
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OKI Semiconductor
ML9361
3. Output pulse width adjustment Output pulse width of anode drive signal output pins (OUT1 to OUT128) can be adjusted for each output pin. Adjustment of each output pulse width is made by 4-bit data PADJ0-n, PADJ1-n, PADJ2-n, and PADJ3-n. This 4-bit data is written in the shift register at the rising edge of the D-CLK signal and latched at the rising edge of the STB signal. An anode drive signal output pin is configured as constant current output until the number of A-CLK pulses becomes equal to the output data of 4 bits of PADJ0-n, PADJ1-n, PADJ2-n, and PADJ3-n. When they have matched, the output becomes low or high impedance at the rising edge of the A-CLK pulse that has matched the output data of PADJ0-n, PADJ1-n, PADJ2-n, and PADJ3-n. Relation between PADJ0-n, PADJ1-n, PADJ2-n, and PADJ3-n and output pulse width is shown below.
PADJ3-n 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PADJ2-n 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PADJ1-n 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PADJ0-n 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output pulse width 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Setting of Output Condition When Dot is OFF The output condition when dot is OFF is set with the combination of HZ, ALL L, OFF HZ, A0 HZ, and P L signals. See "3. Operation of Output Section" in "FUNCTION TABLE" and the section of "OUTPUT WAVEFORMS".
Power Applying Sequence It is possible to apply power first to VDD or VDISP. When power is applied to VDISP, and VDD is 2.5 V or less, following operating states occur. * Constant current source circuit does not operate. * Anode drive signal output pins (OUT1 to 128) become high impedance. Make the RESET pin high at least 250 ns after applying power to VDD. (Refer to RESET execution time in AC Characteristics.)
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PEDL9361-01
OKI Semiconductor
ML9361
REVISION HISTORY
Document No.
PEDL9361-01
Date
Dec. 12, 2002
Page Previous Current Edition Edition
- -
Description
Preliminary edition 1
18/19
PEDL9361-01
OKI Semiconductor
ML9361
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
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